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Bureau of Labor Statistics > Producer Price Indexes > Methods > Quality Adjustment

PPI Introduces Hedonic Price Estimation for Server Microprocessors

Effective with the release of Producer Price Index (PPI) data for July 2018 on August 9, 2018, the Bureau of Labor Statistics began using hedonic modeling to estimate quality adjusted prices for server microprocessor items within the PPI indexes for integrated microcircuits:

Server microprocessors are subject to rapid technological change. This makes it difficult to perform quality adjustment, which requires distinguishing price changes arising from changes in microprocessor quality from price changes resulting from other factors. The following characteristics are the main measures of quality for microprocessors. PPI collects information pertaining to these measures from publicly available sources:

Cores
Threads
Base frequency
Turbo frequency
Cache¹
Thermal design power (TDP)

Beginning with this release, PPI is using a two-period time dummy hedonic model to measure quality-adjusted price change for server microprocessor items in the integrated microcircuits indexes. The basic regression formula is shown in Equation 1, and the results for July 2018 are shown in Table 1.

Equation 1

Log Price_it = Α₀ + Δd_Τ+1 + Β₂ (Log X_2i) + Β₃ (Log X_3i) + … + Β_k (Log X_ki) + Μ_it

Where:

Log Price_it is the Log price of the ith product in period t

Α₀ is the intercept

Log X_i are the logged variables representing product characteristics

d_Τ+1 is the indicator for period two

Δ is the time dummy coefficient

Β₂ … Β_k are the regression/slope coefficients

Μ_it is the residual or error term

The two periods in the model are adjacent quarters. The time dummy coefficient gives an estimate of price change between the two quarters when the variables representing product characteristics have been controlled for. The product characteristics that may be included in the model are those listed above. Cache is divided by the number of cores in the microprocessor. The SPEC² benchmark is also included in the model. In addition, quadratic terms for base frequency, cores, SPEC, and the interaction of SPEC and cores, are included.

The choice of regressors affects the time dummy coefficient estimate. PPI turned to statistical learning to evaluate objectively the performance of different model specifications. Specifically, PPI used repeated cross-validation to calculate the mean squared error (MSE) for different model specifications. The MSE is calculated by using a model to predict the prices of observations and then finding the differences between the predictions and the actual prices. PPI selected the model with the lowest MSE because the lower the MSE, the better predictive performance of the model. Please note that PPI constrained the SPEC variable to be in the model because performance benchmarks can capture improvements in microprocessors that are not captured by the other characteristics.

Table 1. PPI hedonic model regression results for server microprocessors
for July 2018
Variables	18Q2-18Q3
Quarter Dummy	0.0000 (0.0599)
log SPEC	1.3833 (*) (0.1638)
log Cores	-2.1678 (*) (0.9079)
log Threads
log Base Frequency
log Turbo Frequency
log (Cache/Cores)	1.5899 (*) (0.211)
log TDP
(log Base Frequency)²
(log Cores)²	0.5826(*) (0.1542)
(log SPEC)²
log SPEC:log Cores

Observations	102
Adjusted R²	0.9042
Inflation	0.0000
Footnotes: (*) Significant at the 5 percent level. Standard errors in parentheses.

Using the procedure described above, in addition to the time dummy and performance benchmark variables, three variables were selected. The model estimates that prices are unchanged for server microprocessors.

PPI plans to re-estimate the hedonic server microprocessors model quarterly. Each time the model is re-estimated, the specification selection method for variable selection will be used. This may cause the model specification to change from quarter to quarter.

Learn more about the use of hedonic models in the PPI »

For further information on PPI data for integrated microcircuits, contact Steven Sawyer at sawyer.steven@bls.gov or (202) 691-7845.

Footnotes

1 Cache is divided by the number of cores in the microprocessor.

2 The SPEC CPU2017 benchmark is used. For each microprocessor, the median of the SPECrate integer results and the median of the SPECrate floating point results are calculated. These two values are then geometrically averaged, which yields a composite benchmark value.

Last Modified Date: August 9, 2018